Hi, my name is Tom Smykowski, I'm a staff full-stack engineer. I build and scale SaaS platforms to millions of users, working end-to-end from system architecture to frontend to mobile. On this blog I write about software engineering, low-level systems, and the techniques that make infrastructure faster and more predictable
What this article covers
This is a deep dive into Laurie Wired's TailSlayer library and the 60-year-old DRAM design flaw it works around. You get the history of the problem, the technical path she followed from failed prediction to hedged reads, and the benchmark results across AMD, Intel, and Graviton.
Questions this article answers
- Why does DRAM have periodic latency spikes and what causes them?
- What is the tRFC (refresh cycle time) lockout and how large is it?
- How does TailSlayer use hedged reads at the nanosecond scale?
- Why does single-core hedging fail and how multicore fixes it?
- What role do huge pages and XOR channel hashing play?
- Which architectures benefit and by how much?
- Where does this matter in practice and where does it not?
Length and time
A full technical article with diagrams, source-code highlights, and step-by-step setup instructions. Roughly a 10-minute read at moderate pace.